Pass majority of rockwrestler tests

Grarak · Grarak · commit 53f23ac3290d · 2025-05-05T08:32:22.000+02:00
diff --git a/src/jit/disassembler/alu_instructions.rs b/src/jit/disassembler/alu_instructions.rs
@@ -379,10 +379,10 @@ mod alu_ops {
 
     #[inline]
     pub fn smlalbb(opcode: u32, op: Op) -> InstInfo {
-        let op0 = Reg::from(((opcode >> 16) & 0xF) as u8);
-        let op1 = Reg::from((opcode & 0xF) as u8);
-        let op2 = Reg::from(((opcode >> 8) & 0xF) as u8);
-        let op3 = Reg::from(((opcode >> 12) & 0xF) as u8);
+        let op0 = Reg::from(((opcode >> 12) & 0xF) as u8);
+        let op1 = Reg::from(((opcode >> 16) & 0xF) as u8);
+        let op2 = Reg::from((opcode & 0xF) as u8);
+        let op3 = Reg::from(((opcode >> 8) & 0xF) as u8);
         InstInfo::new(
             opcode,
             op,
@@ -417,7 +417,7 @@ mod alu_ops {
             opcode,
             op,
             Operands::new_3(Operand::reg(op0), Operand::reg(op1), Operand::reg(op2)),
-            reg_reserve!(op1, op2),
+            reg_reserve!(op1, op2, Reg::CPSR),
             reg_reserve!(op0, Reg::CPSR),
             1,
         )
diff --git a/src/jit/disassembler/branch_instructions.rs b/src/jit/disassembler/branch_instructions.rs
@@ -27,7 +27,7 @@ mod branch_ops {
                 Op::Blx,
                 Operands::new_1(Operand::imm(op0 as u32)),
                 reg_reserve!(),
-                reg_reserve!(),
+                reg_reserve!(Reg::LR, Reg::PC),
                 1,
             )
         } else {
@@ -47,7 +47,7 @@ mod branch_ops {
                 Op::Blx,
                 Operands::new_1(Operand::imm(op0 as u32)),
                 reg_reserve!(),
-                reg_reserve!(Reg::PC),
+                reg_reserve!(Reg::LR, Reg::PC),
                 1,
             )
         } else {
diff --git a/src/jit/emitter/emit.rs b/src/jit/emitter/emit.rs
@@ -7,7 +7,7 @@ use crate::jit::inst_branch_handler::branch_any_reg;
 use crate::jit::inst_thread_regs_handler::{register_restore_spsr, restore_thumb_after_restore_spsr, set_pc_arm_mode, set_pc_thumb_mode};
 use crate::jit::jit_asm::{debug_after_exec_op, JitAsm, JitRuntimeData};
 use crate::jit::op::Op;
-use crate::jit::reg::Reg;
+use crate::jit::reg::{reg_reserve, Reg};
 use crate::jit::Cond;
 use crate::logging::debug_println;
 use crate::{DEBUG_LOG, IS_DEBUG};
@@ -127,23 +127,29 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
             block_asm.current_pc = start_pc + (((i - start_index) as u32) << pc_shift);
             self.jit_buf.debug_info.record_inst_offset(i, block_asm.get_cursor_offset() as usize);
 
-            if !self.jit_buf.insts[i].op.is_multiple_mem_transfer() {
+            let inst = &self.jit_buf.insts[i];
+            if inst.op.is_multiple_mem_transfer() {
+                let op0 = inst.operands()[0].as_reg_no_shift().unwrap();
+                let op1 = inst.operands()[1].as_reg_list().unwrap();
+                let next_live_regs = self.analyzer.get_next_live_regs(basic_block_index, i);
+                block_asm.alloc_guest_regs(reg_reserve!(op0), op1 & Reg::PC, next_live_regs);
+            } else {
                 self.emit_guest_regs_alloc(i, basic_block_index, block_asm);
             }
 
             let inst = &self.jit_buf.insts[i];
             debug_println!("{:x}: block {basic_block_index}: emit {inst:?}", block_asm.current_pc);
 
+            // if block_asm.current_pc == 0x20076d4 {
+            //     block_asm.bkpt1(0);
+            // }
+
             let mut label = Label::new();
             let needs_cond_jump = !matches!(inst.op, Op::Clz | Op::Qadd | Op::Qsub | Op::Qdadd | Op::Qdsub) && !inst.op.is_alu() && !inst.op.is_mul();
             if inst.cond != Cond::AL && needs_cond_jump {
                 block_asm.b3(!inst.cond, &mut label, BranchHint_kNear);
             }
 
-            // if block_asm.current_pc == 0x20046c4 {
-            //     block_asm.bkpt1(0);
-            // }
-
             if thumb {
                 match inst.op {
                     Op::BlSetupT => {}
@@ -163,10 +169,11 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
                     Op::Mcr | Op::Mrc => self.emit_cp15(i, basic_block_index, block_asm),
                     Op::MsrRc | Op::MsrIc | Op::MsrRs | Op::MsrIs => self.emit_msr(i, basic_block_index, block_asm),
                     Op::MrsRc | Op::MrsRs => self.emit_mrs(i, block_asm),
-                    Op::BlxReg => self.emit_blx(i, basic_block_index, block_asm),
+                    Op::BlxReg => self.emit_blx_reg(i, basic_block_index, block_asm),
                     Op::Bl => self.emit_bl(i, basic_block_index, block_asm),
                     Op::B => self.emit_b(i, basic_block_index, block_asm),
                     Op::Bx => self.emit_bx(i, basic_block_index, block_asm),
+                    Op::Blx => self.emit_blx(i, basic_block_index, block_asm),
                     Op::Swi => self.emit_swi(i, basic_block_index, false, block_asm),
                     Op::Swp | Op::Swpb => self.emit_swp(i, basic_block_index, block_asm),
                     Op::Clz => self.emit_clz(i, block_asm),
diff --git a/src/jit/emitter/emit_alu.rs b/src/jit/emitter/emit_alu.rs
@@ -1,4 +1,5 @@
 use crate::core::CpuType;
+use crate::core::CpuType::ARM9;
 use crate::jit::assembler::block_asm::BlockAsm;
 use crate::jit::assembler::vixl::{
     vixl, MasmClz3, MasmMla5, MasmMlas5, MasmMul4, MasmMuls4, MasmQadd4, MasmQdadd4, MasmQdsub4, MasmQsub4, MasmSmlabb5, MasmSmlabt5, MasmSmlal5, MasmSmlalbb5, MasmSmlalbt5, MasmSmlals5,
@@ -128,6 +129,10 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
     }
 
     pub fn emit_clz(&mut self, inst_index: usize, block_asm: &mut BlockAsm) {
+        if CPU != ARM9 {
+            return;
+        }
+
         let inst = &self.jit_buf.insts[inst_index];
 
         let operands = inst.operands();
@@ -138,6 +143,10 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
     }
 
     pub fn emit_q_op(&mut self, inst_index: usize, block_asm: &mut BlockAsm) {
+        if CPU != ARM9 {
+            return;
+        }
+
         let inst = &self.jit_buf.insts[inst_index];
 
         let operands = inst.operands();
@@ -148,8 +157,8 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
         let func = match inst.op {
             Op::Qadd => <MacroAssembler as MasmQadd4<Cond, Reg, Reg, Reg>>::qadd4,
             Op::Qsub => <MacroAssembler as MasmQsub4<_, _, _, _>>::qsub4,
-            Op::Qdadd => <MacroAssembler as MasmQdadd4<Cond, Reg, Reg, Reg>>::qdadd4,
-            Op::Qdsub => <MacroAssembler as MasmQdsub4<Cond, Reg, Reg, Reg>>::qdsub4,
+            Op::Qdadd => <MacroAssembler as MasmQdadd4<_, _, _, _>>::qdadd4,
+            Op::Qdsub => <MacroAssembler as MasmQdsub4<_, _, _, _>>::qdsub4,
             _ => unreachable!(),
         };
 
diff --git a/src/jit/emitter/emit_branch.rs b/src/jit/emitter/emit_branch.rs
@@ -268,7 +268,7 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
         }
     }
 
-    pub fn emit_blx(&mut self, inst_index: usize, basic_block_index: usize, block_asm: &mut BlockAsm) {
+    pub fn emit_blx_reg(&mut self, inst_index: usize, basic_block_index: usize, block_asm: &mut BlockAsm) {
         let inst = &self.jit_buf.insts[inst_index];
         let op0 = inst.operands()[0].as_reg_no_shift().unwrap();
         let op0_mapped = block_asm.get_guest_map(op0);
@@ -334,6 +334,27 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
         }
     }
 
+    pub fn emit_blx(&mut self, inst_index: usize, basic_block_index: usize, block_asm: &mut BlockAsm) {
+        if CPU != ARM9 {
+            return;
+        }
+
+        let inst = &self.jit_buf.insts[inst_index];
+        let relative_pc = inst.operands()[0].as_imm().unwrap() as i32 + 8;
+        let target_pc = (block_asm.current_pc as i32 + relative_pc) as u32;
+
+        let pc_reg = block_asm.get_guest_map(Reg::PC);
+        block_asm.ldr2(pc_reg, target_pc | 1);
+
+        let lr_reg = block_asm.get_guest_map(Reg::LR);
+        let pc = block_asm.current_pc;
+        block_asm.mov2(lr_reg, &(pc + 4).into());
+        block_asm.add_dirty_guest_regs(reg_reserve!(Reg::LR, Reg::PC));
+        block_asm.save_dirty_guest_regs(true, inst.cond == Cond::AL);
+
+        self.emit_branch_external_label(inst_index, basic_block_index, target_pc | 1, true, block_asm);
+    }
+
     extern "C" fn debug_branch_label(current_pc: u32, target_pc: u32) {
         branch_println!("{CPU:?} branch label from {current_pc:x} to {target_pc:x}")
     }
diff --git a/src/jit/emitter/emit_psr.rs b/src/jit/emitter/emit_psr.rs
@@ -1,7 +1,7 @@
 use crate::core::CpuType;
-use crate::jit::assembler::block_asm::{BlockAsm, CPSR_TMP_REG};
-use crate::jit::assembler::vixl::vixl::{FlagsUpdate_DontCare, SpecialRegisterType_CPSR};
-use crate::jit::assembler::vixl::{MasmAnd3, MasmBic3, MasmMov4, MasmMrs2, MasmOrr3};
+use crate::jit::assembler::block_asm::{BlockAsm, CPSR_TMP_REG, GUEST_REGS_PTR_REG};
+use crate::jit::assembler::vixl::vixl::{FlagsUpdate_DontCare, MaskedSpecialRegisterType_CPSR_f, MemOperand, SpecialRegisterType_CPSR};
+use crate::jit::assembler::vixl::{MasmAnd3, MasmLdrh2, MasmMov4, MasmMrs2, MasmMsr2, MasmOrr3};
 use crate::jit::inst_info::Operand;
 use crate::jit::inst_thread_regs_handler::{register_set_cpsr_checked, register_set_spsr_checked};
 use crate::jit::jit_asm::JitAsm;
@@ -33,6 +33,8 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
         block_asm.mov4(FlagsUpdate_DontCare, Cond::AL, Reg::R1, &flags.into());
         block_asm.call(func);
 
+        block_asm.msr2(MaskedSpecialRegisterType_CPSR_f.into(), &Reg::R0.into());
+
         let next_live_regs = self.analyzer.get_next_live_regs(basic_block_index, inst_index);
         block_asm.restore_tmp_regs(next_live_regs);
 
@@ -47,10 +49,9 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
 
         match inst.op {
             Op::MrsRc => {
-                block_asm.load_guest_reg(Reg::R1, Reg::CPSR);
+                block_asm.ldrh2(Reg::R1, &MemOperand::reg_offset(GUEST_REGS_PTR_REG, Reg::CPSR as i32 * 4));
                 block_asm.mrs2(CPSR_TMP_REG, SpecialRegisterType_CPSR.into());
-                block_asm.bic3(Reg::R1, Reg::R1, &0xFF000000u32.into());
-                block_asm.and3(CPSR_TMP_REG, CPSR_TMP_REG, &0xFF000000u32.into());
+                block_asm.and3(CPSR_TMP_REG, CPSR_TMP_REG, &0xF8000000u32.into());
                 block_asm.orr3(op0_mapped, Reg::R1, &CPSR_TMP_REG.into());
             }
             Op::MrsRs => block_asm.load_guest_reg(op0_mapped, Reg::SPSR),
diff --git a/src/jit/emitter/emit_transfer.rs b/src/jit/emitter/emit_transfer.rs
@@ -166,7 +166,6 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
 
     pub fn emit_multiple_transfer(&mut self, inst_index: usize, basic_block_index: usize, block_asm: &mut BlockAsm) {
         let inst = &self.jit_buf.insts[inst_index];
-        let next_live_regs = self.analyzer.get_next_live_regs(basic_block_index, inst_index);
 
         let transfer = match inst.op {
             Op::Ldm(transfer) | Op::LdmT(transfer) | Op::Stm(transfer) | Op::StmT(transfer) => transfer,
@@ -176,8 +175,6 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
         let op0 = inst.operands()[0].as_reg_no_shift().unwrap();
         let mut op1 = inst.operands()[1].as_reg_list().unwrap();
 
-        block_asm.alloc_guest_regs(reg_reserve!(op0), op1 & Reg::PC, next_live_regs);
-
         let op0_mapped = block_asm.get_guest_map(op0);
         let op1_len = op1.len();
 
@@ -188,6 +185,8 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
             let fast_mem_start = block_asm.get_cursor_offset();
             block_asm.nop0();
             block_asm.mov4(FlagsUpdate_DontCare, Cond::AL, Reg::R0, &op0_mapped.into());
+            block_asm.ldr2(Reg::R2, !0xF0000003);
+            block_asm.and5(FlagsUpdate_DontCare, Cond::AL, Reg::R0, Reg::R0, &Reg::R2.into());
             block_asm.load_mmu_offset(Reg::R1);
             block_asm.add5(FlagsUpdate_DontCare, Cond::AL, Reg::R0, Reg::R0, &Reg::R1.into());
 
@@ -297,6 +296,7 @@ impl<const CPU: CpuType> JitAsm<'_, CPU> {
             block_asm.call(func);
         }
 
+        let next_live_regs = self.analyzer.get_next_live_regs(basic_block_index, inst_index);
         block_asm.restore_tmp_regs(next_live_regs);
         block_asm.reload_active_guest_regs();
     }
diff --git a/src/jit/inst_thread_regs_handler.rs b/src/jit/inst_thread_regs_handler.rs
@@ -1,14 +1,16 @@
 use crate::core::CpuType;
 use crate::get_jit_asm_ptr;
 
-pub unsafe extern "C" fn register_set_cpsr_checked<const CPU: CpuType>(value: u32, flags: u8) {
+pub unsafe extern "C" fn register_set_cpsr_checked<const CPU: CpuType>(value: u32, flags: u8) -> u32 {
     let asm = get_jit_asm_ptr::<CPU>();
     (*asm).emu.thread_set_cpsr_with_flags(CPU, value, flags);
+    (*asm).emu.thread[CPU].cpsr
 }
 
-pub unsafe extern "C" fn register_set_spsr_checked<const CPU: CpuType>(value: u32, flags: u8) {
+pub unsafe extern "C" fn register_set_spsr_checked<const CPU: CpuType>(value: u32, flags: u8) -> u32 {
     let asm = get_jit_asm_ptr::<CPU>();
     (*asm).emu.thread_set_spsr_with_flags(CPU, value, flags);
+    (*asm).emu.thread[CPU].cpsr
 }
 
 pub unsafe extern "C" fn register_restore_spsr<const CPU: CpuType>() {
