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Omit shift when zero
1 parent 0b7c197 commit befc184

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src/jit/assembler/block_asm.rs

+7-1
Original file line numberDiff line numberDiff line change
@@ -216,7 +216,13 @@ impl BlockAsm {
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};
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match value {
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ShiftValue::Reg(shift_reg) => unsafe { vixl::Operand::new5(map_reg, shift_type.into(), self.reg_alloc.get_guest_map(*shift_reg).into()) },
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ShiftValue::Imm(shift_imm) => unsafe { vixl::Operand::new4(map_reg, shift_type.into(), *shift_imm as u32) },
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ShiftValue::Imm(shift_imm) => {
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if *shift_imm == 0 {
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unsafe { vixl::Operand::new2(map_reg) }
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} else {
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unsafe { vixl::Operand::new4(map_reg, shift_type.into(), *shift_imm as u32) }
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}
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}
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}
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}
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}

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