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@riscv-non-isa

RISC-V Non-ISA Specifications

The Open-Standard Instruction Set Architecture
README.md

Welcome to the RISC-V Non-ISA Specifications 👋

RISC-V Logo

Non-ISA specifications do not add new instructions, create or change opcodes, or in any way modify the RISC-V ISA. They do help us to develop an ecosystem around the ISA Specifications.

Things you'll find here include:

  • ABI Documentation
  • Architecture Tests
  • Specifications like Debug, Processor Trace, and Software Interrupts

If you don't find what you're looking for here, try one of our other GitHub organizations:

Popular repositories Loading

  1. riscv-asm-manual riscv-asm-manual Public

    RISC-V Assembly Programmer's Manual

    Makefile 1.5k 249

  2. riscv-elf-psabi-doc riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    Python 775 168

  3. riscv-arch-test riscv-arch-test Public

    Assembly 560 226

  4. riscv-sbi-doc riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    Makefile 403 95

  5. rvv-intrinsic-doc rvv-intrinsic-doc Public

    C 330 96

  6. riscv-trace-spec riscv-trace-spec Public

    RISC-V Processor Trace Specification

    C 183 53

Repositories

Showing 10 of 34 repositories
  • riscv-trace-spec Public

    RISC-V Processor Trace Specification

    riscv-non-isa/riscv-trace-spec’s past year of commit activity
    C 183 CC-BY-4.0 53 23 5 Updated May 16, 2025
  • riscv-toolchain-conventions Public

    Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains

    riscv-non-isa/riscv-toolchain-conventions’s past year of commit activity
    Makefile 149 CC-BY-4.0 42 10 4 Updated May 15, 2025
  • riscv-external-debug-security Public

    The RISC-V External Debug Security Specification

    riscv-non-isa/riscv-external-debug-security’s past year of commit activity
    Makefile 19 CC-BY-4.0 4 3 0 Updated May 14, 2025
  • riscv-ap-tee Public

    This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the programming interfaces (ABI) to support the Confidential VM Extension (CoVE) confidential computing architecture for RISC-V application-processor platforms.

    riscv-non-isa/riscv-ap-tee’s past year of commit activity
    Makefile 55 CC-BY-4.0 23 21 0 Updated May 13, 2025
  • riscv-iommu Public

    RISC-V IOMMU Specification

    riscv-non-isa/riscv-iommu’s past year of commit activity
    C 116 CC-BY-4.0 21 1 5 Updated May 12, 2025
  • riscv-elf-psabi-doc Public

    A RISC-V ELF psABI Document

    riscv-non-isa/riscv-elf-psabi-doc’s past year of commit activity
    Python 775 CC-BY-4.0 168 58 23 Updated May 12, 2025
  • riscv-arch-test Public
    riscv-non-isa/riscv-arch-test’s past year of commit activity
    Assembly 560 Apache-2.0 226 56 38 Updated May 12, 2025
  • riscv-sbi-doc Public

    Documentation for the RISC-V Supervisor Binary Interface

    riscv-non-isa/riscv-sbi-doc’s past year of commit activity
    Makefile 403 CC-BY-4.0 95 11 5 Updated May 9, 2025
  • riscv-security-model Public

    RISC-V Security Model

    riscv-non-isa/riscv-security-model’s past year of commit activity
    Makefile 30 CC-BY-4.0 17 0 1 Updated May 9, 2025
  • riscv-semihosting Public
    riscv-non-isa/riscv-semihosting’s past year of commit activity
    Makefile 30 CC-BY-SA-4.0 9 0 1 Updated May 9, 2025
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