full-adder

Here are 45 public repositories matching this topic...

nxbyte / Verilog-Projects

This repository contains source code for past labs and projects involving FPGA and Verilog based designs

simulator encoder decoder priority verilog xilinx testbenches multiplexer comparator adder system-verilog xilinx-vivado half-adder traffic-light-controller full-adder ripple-adder look-ahead-adder

Updated Oct 2, 2019
Verilog

Elidevin / nandgame.com-solutions

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Solutions for NandGame.com

Updated Oct 5, 2023

luckykadam / adder

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Binary Adder using RNN in Keras

tensorflow keras recurrent-neural-networks full-adder binary-addition

Updated Jul 21, 2020
Jupyter Notebook

bespoyasov / binary-full-adder-in-the-game-of-life

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Binary adder implementation in the Game of Life written in JavaScript using canvas.

tutorial game-of-life digital-logic half-adder full-adder

Updated Jan 25, 2025
JavaScript

Stavros / Multiplier4bit

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A 4bit Multiplier in VHDL

fpga vhdl half-adder vhdl-code vhdl-examples full-adder

Updated Feb 3, 2020
VHDL

MohammadNiknam17 / Signed-4BIT-Binary-Multiplier_VHDL-FPGA

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These are VHDL codes for a signed 4bit multiplier using 4bit adders. Base on Baugh-Wooley Method.

fpga binary vhdl signed fulladder 4bit multiplier halfadder vhdl-code full-adder baugh-wooley

Updated May 10, 2021
VHDL

mcquerol / electronic-systems

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Various electronic systems including ADC/DAC, filters, and simulations using NI Multisim.

Updated Apr 16, 2025

Vedant-02 / Verilog-HDL-Lab-Experiments

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Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

Updated Oct 23, 2022
Verilog

Keerthiraj-Nagaraj / IBM-quantum-challenge-2020

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My solutions to 5 exercises of IBM quantum challenge 2020. Topics include quantum full-adder circuit implementation, circuit optimization and solving various puzzles using Grover's search algorithm.

quantum-computing quantum-gates asteroids-game ibm-quantum-experience qiskit grovers-algorithm full-adder lights-out-game ibm-quantum-challenge quantum-gate-optimization

Updated Dec 7, 2020
Jupyter Notebook

utkarshad21 / 4-bit-Full-Adder-using-Verilog-HDL

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Verilog code and testbench for 4-bit full adder

verilog adder full-adder verilog-project verilog-code 4-bit-adder

Updated Jul 11, 2024
Verilog

MohammadNiknam17 / vending_machine_processor

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VHDL codes for 8-bit Vending Machine Processor, support for two drinks & three types of coins. contains: fsm, Accumulator, comparator, subtractor, mux, Adder, etc.

fsm fpga processor vhdl mux vendingmachine comparator accumulator vending-machine vhdl-code full-adder

Updated Jul 20, 2021
VHDL

ammarmalik17 / Verilog_Adders

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This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.